1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to an apparatus and a method of generating a DBI signal in a semiconductor memory apparatus.
2. Related Art
A DBI (Data Bus Inversion) system is used in order to prevent a problem, such as simultaneous switching noise or inter symbol interference, that occurs as the number of data bits to be switched increases upon data transmission, that is, as the number of currently switched data bits among the entire data bits becomes larger than the number of previously switched data bits.
In the DBI system, in order to solve the above problem, when the number of switched data bits is half or more of the number of all data bits, a DBI signal (DBI Flag) is enabled, and inverted data is transmitted, instead of original data, thereby reducing the number of switched data bits to half or less.
Hereinafter, the related art will be described with reference to FIG. 1.
As shown in FIG. 1, an apparatus for generating a DBI signal in a semiconductor memory apparatus according to the related art compares previous data PREV_DATA and current data CURR_DATA, each of which has N+1 bits from 0 to N, using an XOR gate.
When a previous data bit is different from a current data bit, a signal corresponding to the changed bit among signals EVAL<0:N> is enabled and inverted signals EVALB<0:N> of the signals EVAL<0:N> are generated.
At this time, when the previous data bit is consistent with the current data bit, a signal corresponding to the unchanged bit among signals EVALB<0:N> is enabled.
The signals EVAL<0:N> and the inverted signals EVALB<0:N> are correspondingly input to inverter arrays whose output terminals are connected to the same node. The outputs of the individual inverter arrays are input to a negative input terminal (−) and a positive input terminal (+) of a comparator.
At this time, the number of P-type transistors and N-type transistors to be turned on in the inverters varies according to the number of enabled signals among the signals EVAL<0:N> and the inverted signals EVALB<0:N>.
Accordingly, a voltage difference occurs between the negative input terminal (−) and the positive input terminal (+) of the comparator according to a resistance ratio between the P-type transistor and the N-type transistor. The comparator outputs a DBI signal at high level or low level according to the voltage difference.
For example, when N=7 and the number of enabled signals among the signals EVAL<0:N> is four or more, the voltage at the negative input terminal of the comparator becomes lower than the voltage at the positive input terminal thereof, and the DBI signal is enabled (for example, a high level). Otherwise, the DBI signal is disabled, that is, the DBI signal changes to a low level.
However, the apparatus for generating a DBI signal in a semiconductor memory apparatus according to the related art has the following problems.
First, since the outputs of the inverters are connected to the same node, a short circuit current may be generated, thereby increasing current consumption.
Second, there may be an error in DBI signal generation due to resistance skew of a transistor of each inverter, which causes an error in data transfer. As a result, an operation error in a system to which a semiconductor memory apparatus is applied may occur.